`include "defines.v"
module ysyx_210448_MEM_WB (
    input clk,
    input wire rst,
    input wire mem_wb_en,
    input wire mem_write,
    input wire mem_write_ready,
    input wire [63:0]mem_pc,
    input wire [31:0] mem_inst,
    input wire mem_fetched,
    input wire mem_w_ena,
	input wire [4:0] mem_rd,
	input wire [`REG_BUS] mem_data,
    input wire mem_read,
    input wire [63:0]mem_read_data,
    input wire [11:0]mem_csr,
    input wire mem_csr_write,
	input wire mem_csr_read,
    input wire [63:0] mem_csr_data,
    input wire [6:0] mem_opcode,
    input wire mem_open,
    input wire close,
    input wire mem_skip,
    input wire mem_csr_skip,

    output reg [63:0]wb_pc,
    output reg [31:0] wb_inst,
    output reg wb_fetched,
    output reg wb_write_ready,
    output reg wb_w_ena,
    output reg wb_write,
	output reg [4:0] wb_rd,
	output reg [`REG_BUS] wb_data,
    output reg wb_read,
    output reg [63:0]wb_read_data,
    output reg [11:0]wb_csr,
    output reg wb_csr_write,
	output reg wb_csr_read,
    output reg [63:0] wb_csr_data,
    output reg [6:0] wb_opcode,
    output reg wb_open,
    output reg wb_skip,
    output reg wb_close,
    output reg wb_csr_skip
);

    always @(posedge clk) begin
      if(rst==1'b1)
        begin
        wb_pc<=64'b0;
        wb_inst<=32'b0;
        wb_w_ena<=1'b0;
	    wb_rd<=5'b0;
	    wb_data<=64'b0;
        wb_read<=1'b1;
        wb_read_data<=64'b0;
        wb_csr<=12'b0;
        wb_csr_write<=1'b0;
	    wb_csr_read<=1'b0;
        wb_csr_data<=64'b0;
        wb_opcode<=7'b0;
        wb_open<=1'b0;
        wb_skip<=1'b0;
        wb_csr_skip<=1'b0;
        wb_fetched<=1'b0;
        wb_close<=1'b0;
        wb_write<=1'b0;
        wb_write_ready<=1'b0;
        end
        else if(mem_wb_en)
        begin
        wb_pc<=mem_pc;
        wb_inst<=mem_inst;
        wb_w_ena<=mem_w_ena;
	    wb_rd<=mem_rd;
	    wb_data<=mem_data;
        wb_read<=mem_read;
        wb_read_data<=mem_read_data;
        wb_csr<=mem_csr;
        wb_csr_write<=mem_csr_write;
	    wb_csr_read<=mem_csr_read;
        wb_csr_data<=mem_csr_data;
        wb_opcode<=mem_opcode;
        wb_open<=mem_open;
        wb_skip<=mem_skip;
        wb_csr_skip<=mem_csr_skip;
        wb_fetched<=mem_fetched;
        wb_close<=close;
        wb_write<=mem_write;
        wb_write_ready<=mem_write_ready;
        end
    end
endmodule
